Electronic device comprising a field effect transistor for high-frequency aplications

ABSTRACT

An electronic device comprising a field-effect transistor having an inter digitated structure suitable for high-frequency power applications, and having multiple threshold voltages that are provided in different regions of each a segment of the interdigitated structure. This leads to a dramatic improvement in linearity over a large power range in the back-off region under class AB signal operation.

The invention relates to an electronic device comprising a field effecttransistor provided with a plurality of parallel-connected transistorsegments having mutually different threshold voltages. The invention inparticular relates to a field effect transistor which is suitable foruse with high power levels and high frequencies.

Such a transistor is known from WO-A 02/07223. In this prior arttransistor, at least one group of said transistor segments have athreshold voltage different from that of the rest of the transistorsegments. Within the context of this application, the term segment isunderstood to mean a part of a transistor having finger-shaped gateelectrodes, each finger being a segment. The linearity and theefficiency are improved by varying the threshold voltage. In particular,an LDMOS-type transistor was provided in which one half of thetransistor had a threshold voltage different from that of the otherhalf. The difference between the two threshold voltages wasapproximately 0.3 V. As a result, the intermodulation distortion wasimproved by approximately 3 dB when the transistor was operated at afrequency of 1.8-2.0 GHz and an output power level of 17 dB. Theintermodulation distortion is a measure of the linearity. In a verysimple LDMOS model, only the main source of distortion is taken intoaccount, namely the non-linearity in the transfer characteristic (theIds-Vgs characteristic). The distortion is built up of a number of termsin that case, which are the higher derivatives of the transconductance.A more detailed explanation of the intermodulation distortion concept isknown inter alia from Van der Heijden et al. IEEE Transactions onMicrowave Theory and Techniques, Vol. 50, No. 9, September 2002, pp2176-2184.

During experiments that led to the invention it was found that the factthat a first group of segments have a threshold voltage different fromthat of a second group of segments in itself does not suffice forachieving an improved linearity whilst retaining or improving theefficiency level. In particular it was found that an LDMOS transistorcomprising a first, a second and a third group of segments, each havingtheir own threshold voltage, does not exhibit any relevant improvementas regards the linearity or the efficiency at all. In these experiments,the differences between the threshold voltages in the various segmentsgenerally varied between 0.1 V and 1.5 V in comparison with anon-distributed device.

For this reason it is an object of the invention to provide a transistorof the kind referred to in the introduction, in which a linearityimprovement in the back-off region is realized whilst retaining orimproving the efficiency level, and in which the obtained device can beupscaled to higher power levels. As a result, the back-off region ischaracterized by the use of a power level lower than the maximum powerlevel. As a result of the use in the back-off region, a sufficientlylinear transistor behavior is retained also in the case of peak loads.

This object is achieved in that each of the transistor segmentscomprises a first region and a second region, the first region having afirst threshold voltage and the second region having a second thresholdvoltage.

Surprisingly it has been found that if the intermodulation distortion inthe back-off region is to be reduced whilst retaining the sameefficiency level, a transistor segment needs to have different regionshaving different threshold voltages. This is also a condition for easyscalability of the device in question to higher power levels.

The parallel connection of the gate electrodes of the non-uniformsegments has a positive effect on the gate-drain characteristics. Inparticular the dependence of the current on the drain (I_(d)) as afunction of the voltage on the gate (V_(g)) is concerned here. As aresult of this positive effect, the uneven higher terms of theintermodulation distortion are minimized in the gate voltage range thatis relevant to the desired application. This leads to a significantimprovement in the intermodulation behavior in back-off as a result ofthe linearization of the amplitude transfer characteristics (AM-AMconversion). Not only the third order intermodulation is concerned, butalso the fifth order and seventh order intermodulation. It has beenfound that the AM-AM conversion is influenced in particular by theselected differences in the threshold voltage between the variousregions within a segment.

It has been found that an improved linearity can already be observedwhen two regions per segment are used. Preferably, a segment comprisesthree to five regions, more preferably three regions. The drawback ofusing more than five regions is that he manufacturing costs willstrongly increase.

An advantageous aspect of the transistor according to the invention isthe fact that its design is scalable. After all, the core element is asingle segment, and its functioning appears not to be dependent on thepresence of specific neighboring segments. It is possible, therefore, toadd a number of segments in the design, for example in order to be ableto handle higher power levels. Preferably, at least 20 segments arepresent, preferably 40-100, so as to enable output power levels of morethan 5 W, in particular more than 30 W.

In particular, the scalability is much better than the scalability of atransistor having at least three threshold voltages, in which thethreshold voltage varies among the segments (i.e. a first, a second anda third group of segments). For the optimization of the characteristicsit is necessary for the groups to have different surface areas. Uponvariation of the threshold voltage among the segments, this implies adifferent number of segments per group. Upscaling to higher output powerlevels without any loss of quality can only be realized under specificcircumstances with transistors of that type; that is, when the upscalingfactor is such that it results in a whole number of segments for eachgroup again. In the case of an upscaling factor of, for example, 1.15 or1.33, there is very little chance of achieving this. In the deviceaccording to the invention, however, transistor segments may be added asdesired.

In order to realize a further improvement, it is necessary to linearizethe phase transfer characteristic (AM-PM conversion). Thischaracteristic appears to be strongly influenced by the manner in whichthe various segments are connected and by the manner in which the totalwidth of the gate electrode is distributed over the regions that arepresent. It is in particular advantageous for the threshold voltages tovary between 10 and 40%, preferably between 20 and 30% of the averagethreshold voltage. Within the context of the present application, thevariation of the threshold voltage is understood to mean the differencebetween the lowest and the highest threshold voltage present.

Furthermore it is advantageous if the region having the highestthreshold voltage also comprises the largest surface area. In a segmentcomprising three regions, the area of the first region having thehighest threshold voltage comprises 30 to 70%, the area of the thirdregion having the lowest threshold voltage comprises 20 to 50%, and thearea of the second region comprises 10 to 30%.

Various techniques may be used for generating the difference inthreshold voltage, as is known per se. Examples of such techniques are:variation of the thickness of the gate dielectric, in particular thegate oxide, variation of the doping concentration in the channel, andvariation of the material of the gate electrode and the gate dielectric.

The field effect transistor according to the invention is, for example,a transistor of the laterally diffused metal-oxide semiconductor (LDMOS)type based on a Si or SiC semiconductor substrate. Otherwise, theinventive concept may be realized in transistors formed in so-termedIII-V material, such as GaN, GaAs, InP, and in various transistor types,such as MESFET—in particular HEMT and inverted HEMT, JFET, MODFET andMISFET transistors. The transistor is very suitable for use at highfrequencies, for example in the range from 0.9 to 3 GHz, and at highersupply voltages, for example in the order of 20 to 30 V. Furthermore,one or more transistor segments may be provided with an additional gateelectrode, which are connected to one or more contacts. It has beenfound that the linearity of the device can be improved significantlywith such a contact.

Preferably, the device according to the invention furthermore comprisesa module substrate, on which the transistor is assembled, and animpedance matching circuit is provided for adjusting the outputimpedance of the transistor. Transistors according to the invention arevery suitable for use as amplifiers, for example in mobile communicationand optical network communication applications. As a rule, filters andcircuits for regulating the impedance are used to ensure that thetransistor is properly attuned to aerials or other components that areconnected downstream of the transistor. In the transistor according tothe invention, both the transconductance (AM-AM transfer) and the phase(AM-PM transfer) are optimized. Thus both the real and the imaginaryimpedance component are readily predictable, which simplifies theimpedance matching process. Preferably, a heat sink is present fordissipating any excess heat. Filters and other passive components arepresent on or integrated in the module substrate.

The above and further aspects of the electronic device will now beexplained in more detail with reference to a number of figures, inwhich:

FIG. 1 is a plan view of a semiconductor device;

FIG. 2 is a schematic, cross-sectional view of the device that is shownin FIG. 1, along the line II-II;

FIG. 3 is a schematic, cross-sectional view of a prior art transistor;

FIG. 4 is a plan view of a few segments in the transistor according tothe invention;

FIG. 5 shows an equivalent circuit diagram of the device that is shownin FIG. 4;

FIGS. 6-9 are graphs which show the electric characteristics of thedevice according to the invention and of a prior art device.

The Figures are not drawn true to scale, and in particular the thicknessdimensions are exaggerated for the sake of clarity. Regionscorresponding to each other are indicated by the same reference numeralas much as possible.

FIG. 1 is a plan view of a transistor as present in the device accordingto the invention. FIG. 2 shows the corresponding cross-section along theline II-II in FIG. 1. The device comprises a semiconductor body 1, whichis made of silicon in this example, but which may also be made ofanother suitable semiconductor material, of course. The semiconductorbody is built up of a low-ohmic, highly doped p-type substrate 2 and acomparatively weakly doped, high-ohmic region 3 adjoining the surface ofthe silicon body, in which the transistor is accommodated. In thisexample, the region 3 is formed by a p-type epitaxial layer having athickness of approximately 7 μm and a doping concentration ofapproximately 5.10¹⁵ atoms per cm³. The doping concentration of thesubstrate 2 which functions as a connection for the source zone is high,for example between 10¹⁹ and 10²⁰ atoms per cm³. An active region 6 isdefined in the epitaxial layer, which region is laterally bounded bythick field oxide 7. Source and drain zones of the transistor areprovided in the active region in the form of highly doped n-type surfacezones 4 and 5, respectively. The transistor comprises a segmentstructure comprising a number of adjacent source/drain fingers. Thisstructure may be obtained in a simple manner, for example by extendingthe portion that is shown in FIG. 1 and FIG. 2 to the left and to theright until the desired channel width is obtained. To increase thebreakdown voltage, the drain zone 5 is provided with a high-ohmic n-typedrain extension 8 between the drain zone 5 and the channel of thetransistor. The length of the extension is 3.5 μm in this example. Thetransistor channel is formed by the p-type region 13 between theextension 8 and the source zone 4. A gate electrode 9 is provided abovethe channel, which gate electrode is separated from the channel by agate oxide 10 having a thickness of, for example, 70 nm. The gateelectrode 9 is formed by strips of highly doped, approximately 0.3 μmthick polycrystalline silicon (poly) overlaid with 0.2 μm titaniumsilicide, which, seen at the surface, extends transversely over theactive region 6 between the source zones 4 and the drain extensions 8.The source zone (or zones) 4 is (are) short-circuited with the p-typeregion via a deep, highly doped p-type zone II which extends from thesurface down to the highly doped substrate and which connects the sourcezone 4 to the source electrode 12 at the underside of the substrate viathe substrate 2. The transistor is embodied as an LDMOST, so that it canbe operated at a sufficiently high voltage, for which purpose anadditional p-type doping is provided in the channel in the form of thediffused p-type zone 13, so that the doping concentration is locallyincreased as compared with the weak epi doping.

The surface is coated with a thick glass layer, in which contact windowsare provided above the source and drain zones, through which contactwindows the source and drain zones are connected to metallic source anddrain electrodes 15 and 16, respectively. Said electrodes 15 and 16 areformed by metal strips extending parallel to each other over the glasslayer. The source contact 15 is not only connected to the sourcezone(s), but also to the deep p-type zone 11, and thus interconnects thesource zone and the connection 12 at the underside of the substrate. Thesource zone may be connected to external connections or circuit elementsvia this connection. The drain electrodes 16 together with the baseportion forms a comb structure and they may be connected to a number ofbond pads present elsewhere on the crystal via the common portion 17.

The gate electrode 9 of the device is also provided with a metalcontact, which extends in the form of a strip 18 over the oxide layerbetween the metal strips 15 and 16, and which is locally connected tothe gate 9 via contact windows in the oxide layer 14. The metal track 18is not connected to the gate 9 over its entire length, but only at anumber of interspaced locations 19, at which the poly gate 9 is providedwith widened portions suitable for connections. If the interspacingsbetween the connections 19 are sufficiently small, the gate resistanceis significantly reduced by the presence of the metal tracks 18. Theresistance of the gate electrode is also reduced by the presence oftitanium silicide thereon. A very low gate resistance can be obtainedthrough the use of a metal having a low resistivity, for example gold oraluminum. Further metal tracks 20 are provided between the metal or, inthis case, metal silicide tracks 18 and the drain contact tracks, whichfurther metal tracks form a capacitive screen between the gate 9,18 andthe drain electrode 16. The screening tracks 20 are connected to thesource electrode 15 beyond the peaks of the metal tracks 18 viaconnections 21, and to the connection of the source via said electrode.

FIG. 3 is a further cross-sectional view of the device according to theprior art, showing a number of parallel segments A, B, C having mutuallydifferent threshold voltages. The differences in the threshold voltageshave been realized in this case by varying the thickness of the gateoxide 10 (10A, 10B, 10C). The connecting contacts are not shown forreasons of simplicity of the drawing.

FIG. 4 is a schematic plan view of the device according to theinvention, in which a transistor 1 comprising several segments A, B, Cis shown.

FIG. 5 shows a corresponding electric diagram. The connecting contactsfor the gate electrode V_(g) and the drain electrode V_(d) exhibitself-inductance at frequencies of 2 GHz. The drain electrode isconnected to earth via a capacitor and an impedance Z_(L). The sourceelectrode is connected to a contact via an impedance Z_(s).

In the embodiment shown, all segments have the same layout, comprising afirst region 51, a second region 52 and a third region 53. The basicthreshold voltage is in the order of 3-3.5 V in this embodiment, withvariations between the regions of 10-15%. The first region comprises asurface area of 40-50%, the second region comprises a surface area of15-25%, and the third region comprises a surface area of 30-40%, thetotal being 100%. At an average power P₀-avg of 30 dBm, the followingvalues are found for the intermodulation distortions: IMD3−52 dBc;IMD5−72 dBc and IMD7<−80 dBc. A 13 dB gain was obtained.

The measurements took place at a frequency of 2 GHz, T=20° C.,I_(dq)=270 mA and a load line of 46 dBm (40 W) and a source-drainvoltage V_(ds) of 26 (V). The same measurements were carried out with abasic threshold voltage in the order of 4.5-5.0 V and a larger gateoxide thickness, with comparable results being obtained.

By way of comparison, measurements were carried out in the aboveconditions on a comparable transistor having a uniform threshold voltageof 4.9 V. The following values were obtained: IMD3−46 dBc; IMD5−53 dBcand IMD7−65 dBc. A 13 dB was obtained.

FIG. 6 shows the AM-AM conversion and the AM-PM conversion as functionsof an input power for the device according to the invention. FIG. 7shows the same data for a prior art device, in particular the transistorwith the aforesaid index numbers. A linearity-characterizing complexmagnitude is S21, the large signal transducer gain which is defined asthe ratio between the forward wave at the output and the forward wave atthe input, can be represented as r.e^(i)*^(φ). The magnitude of the gainMag S21 (in dB) is plotted on one y-axis, and the normalized argument(the angle) of the gain Arg S21 (in degrees) is plotted on the othery-axis. Upon comparison it becomes apparent that the gain in thetransistor according to the invention is more linear both as regards themagnitude and as regards the angle over a large range of input powerlevels (P_(in) as determined by means of a Network Analyser (NWA)) from6 to 15 dBm.

FIG. 8 shows the uneven order of the intermodulation IMD3, IMD5, IMD7 asa function of the average output voltage for the device according to theinvention. FIG. 9 shows the same data for the prior art device. From thecomparison it becomes apparent that the intermodulation distortion inthe device according to the invention is significantly lower. Whereasthe IMD3 level increases to more than −50 dB at 23 dBm already in theprior art device, the IMD3, the IMD5 as well as the IMD7 levels remainbelow −50 dB up to values of 39 dBm in the device according to theinvention.

1. An electronic device comprising a field effect transistor providedwith a plurality of parallel-connected transistor segments havingmutually different threshold voltages, characterized in that each of thetransistor segments comprises a first region and a second region, thefirst region having a first threshold voltage and the second regionhaving a second threshold voltage.
 2. An electronic device as claimed inclaim 1, characterized in that each of the transistor segments alsocomprises a third region having a third threshold voltage, which islower than the second threshold voltage.
 3. An electronic device asclaimed in claim 1, characterized in that the difference between thefirst and the second threshold voltage amounts to 5-20% of the averagethreshold voltage.
 4. An electronic device as claimed in claim 2,characterized in that the difference between the second and the thirdthreshold voltage amounts to 5-20% of the average threshold voltage. 5.An electronic device as claimed in claim 3, characterized in that thedifference in the threshold voltage amounts to 10-15% of the averagethreshold voltage.
 6. An electronic device as claimed in claim 2,characterized in that the first region comprises 40-60% of the surfacearea of the segment.
 7. An electronic device as claimed in claim 1,characterized in that the field effect transistor is a MOS transistor,which is defined in a semiconductor body comprising highly doped sourceand drain zones and a channel region extending between the source zoneand the drain zone, with a gate electrode being present which overlapsthe channel region upon perpendicular projection thereon, in which thesource zone, the drain zone and the gate electrode are connected on thesurface to a metal source contact, a drain contact and a gate electrodecontact, respectively, in which the semiconductor body comprises acomparatively weakly doped region of a first conductivity type adjoiningthe surface, which region comprises the highly doped source and drainzone of the opposite, second conductivity type and a weakly doped drainextension between the drain zone and the channel region, in which thegate electrode is electrically insulated from the channel region and inwhich an electrically insulating layer is laid over the surface, whichlayer has contact windows above the source zone, the drain zone and thegate electrode, through which contact windows the source zone, the drainzone and the gate electrode, respectively, are connected to thecontacts.
 8. An electronic device as claimed in claim 7, characterizedin that another metal strip is present between the gate electrodecontact and the drain contact, which strip is electrically insulatedfrom the semiconductor body and which is locally connected to the sourcestrip via an electrical connection, and which form a screen between thegate electrode contact and the drain contact.
 9. An electronic device asclaimed in claim 1, characterized in that the field effect transistor isused as an amplifier and is assembled on a carrier provided with animpedance matching circuit that is connected to the output of the fieldeffect transistor.
 10. An electronic device as claimed in claim 1,characterized in that the field effect transistor can be operated as anclass AB amplifier.